1. Field of the invention
The present invention relates to a method and circuit for detecting a data error. More specifically, the present invention relates to a data error detecting circuit incorporated in a signal processing circuit which is used in a compact disc (CD) player.
2. Description of the prior art
In a CD player, an 8-bit symbol is produced based upon data which is read from a disc in the form of an EFM signal such that music signal data can be reproduced; however, there is possibility that a data error occurs in the symbol. Such a data error originates in a defect which takes place when pits are written on the disc, a defect due to a wound which takes place in handling the disc, or a defect due to fluctuation or disturbance of a mechanical characteristic of the player. Therefore, in the CD player, in order to detect and correct such a data error, a system called a Cross Interleave Reed-Solomon Code (CIRC) is utilized.
For better understanding of the present invention, the system is described in outline. First, in the case where the data is recorded on the disc, right channel data and left channel data each including 16-bit music signal data of 6 in total are divided into 8-bit symbols, and therefore, 24 symbols in total are produced. After selectively delaying and re-composing these symbols, parity data Q.sub.0, Q.sub.1, Q.sub.2 l and Q.sub.3 (each being 8 bits) of C.sub.2 are added to the symbols in accordance with a Reed-Solomon Code method, becoming 28 symbols in total. The 28 symbols are further delayed by a time period different from each other, respectively, and parity data P.sub.0, P.sub.1, P.sub.2 and P.sub.3 (each being 8 bits) of C.sub.1 are also added to the 28 symbols in accordance with the Reed-Solomon Code method, becoming 32 symbols in total. Then, the 32 symbols are selectively delayed and the parity data Q.sub.0, Q.sub.1, Q.sub.2 and Q.sub.3, and P.sub.0, P.sub.1, P.sub.2 and P.sub.3 are inverted such that the symbols become a group of data to be written, and thereafter, such a group of data are modulated in a form of an EFM (Eight to Fourteen Modulation) and recorded on the disc together with synchronization signals.
In reproducing the disc, the 8-bit symbols of 32 in total are produced from an EFM signal which is read from the disc, such symbols are conducted in the reverse process of the above described writing process. More specifically, the 32 symbols are selectively delayed and the parity data Q.sub.0, Q.sub.1, Q.sub.2 and Q.sub.3, and P.sub.0, P.sub.1, P.sub.2 and P.sub.3 are inverted, and thereafter, the symbols are C.sub.1 -decoded, becoming 28 symbols in total. In C.sub.1 -decoding process, a syndrome is calculated based upon the respective symbols, and error detection and correction is made based upon such a calculated syndrome in accordance with the Reed-Solomon Code method. Furthermore, the 28 symbols being C.sub.1 -decoded are C.sub.2 -decoded after selectively delaying the same, becoming 24 symbols in total. As similar to the C.sub.1 -decoding process, in the C.sub.2 -decoding process, a syndrome is calculated based upon the respective symbols, and error detection and correction is made based upon such a calculated syndrome in accordance with the Reed-Solomon Code method. Then, the 24 symbols after C.sub.2 -decoding process are re-composed and selectively delayed, being restored to the original music signal data.
In addition, the CD system which utilizes a Cross Interleave Reed-Solomon Code method has been well known, and therefore, a more detailed description will be omitted here.
Conventionally, in the case where a data error is to be detected in accordance with the Reed-Solomon Code method, syndromes are calculated in accordance with the following equation (1). ##EQU1## where, .alpha. is a root of a polynomial of degree eight as follows: EQU F(X)=X.sup.8 +X.sup.4 +X.sup.3 +X.sup.2 +1
As a result of the above described calculation, if all of the syndromes S.sub.0, S.sub.1, S.sub.2 and S.sub.3 are "0", it is detected that no errors occur, that is, error zero.
On the other hand, in the case where a data error occurs in only the j-th data D.sub.j, such a data error can be detected by determining whether or not relationship set forth in the following can be formed: EQU S.sub.1.sup.2 =S.sub.0 .multidot.S.sub.2, S.sub.2.sup.2 =S.sub.1 .multidot.S.sub.3 EQU S.sub.0 .noteq.0, S.sub.1 .noteq.0, S.sub.2 .noteq.=0, S.sub.3 .noteq.0
and, a position where the data error occurs (error position) can be evaluated by calculating S.sub.1 /S.sub.0 =.alpha..sup.j and a logarithm thereof.
Furthermore, in the case where data errors occur in the data D.sub.j and D.sub.i, since the following equations can be formed, by evaluating j and i, it is possible to detect that data errors occur. EQU .alpha..sup.j +.alpha..sup.i =(S.sub.1 .multidot.S.sub.2 +S.sub.0 .multidot.S.sub.3)/(S.sub.1.sup.2 +S.sub.0 .multidot.S.sub.2) EQU .alpha..sup.i .multidot..alpha..sup.j =(S.sub.2.sup.2 +S.sub.1 .multidot.S.sub.3)/(S.sub.1.sup.2 +S.sub.0 .multidot.S.sub.2) EQU 0.ltoreq.j, i.ltoreq.31, j.noteq.i
Furthermore, in accordance with the following equation, error components E.sub.j and E.sub.i can be evaluated. ##EQU2##
As to data error detection and correction in the CD by means of the above described Reed-Solomon Code method, more detail description was made in Japanese Patent Application Laid-open No. 77529/1985.
In a circuit in which the above described data error detection and correction can be performed, there were disadvantages that a ROM for converting the data into a logarithm and a number of multiplying and dividing circuits become necessary, that especially, in detecting double errors, since it is necessary to repeatedly execute multiplication and division, it takes a long time to detect data errors and to calculate error positions, and that the number of timing signals necessary for calculation becomes large.